(1) Field of the Invention
This invention relates to an analog switch circuit for sampling an analog signal and, more particularly, to an analog switch circuit having a voltage boost circuit for boosting the potential of a gate of a MOS field effect-transistor included in an analog switch.
(2) Description of the Related Art
Sample and hold circuits are important elements in analog-to-digital (A/D) converters which can be fabricated at a comparatively low cost by a complementary metal-oxide semiconductor (CMOS) process. With CMOS large scale integrated circuits (LSIs), usually an analog switch (or a transfer gate) is used for sampling an analog signal.
With the progress of microfabrication technologies and the spread of battery-operated equipment, it is greatly hoped that not only circuits but also analog switches (transfer gates) will operate at low voltage.
Unlike digital circuits, however, the potential of the source and drain electrodes of metal oxide semiconductor (MOS) field effect transistors included in analog switches etc. used for sampling can be about half (VDD/2) of power supply voltage (VDD) Therefore, voltage between a gate and a source is small compared with digital circuits and it is difficult for analog switches to operate at low voltage.
In these circumstances, some improvements have been suggested to make analog switches operate at low voltage.
For example, Japanese Unexamined Patent Publication No. 7-74638, Japanese Unexamined Patent Publication No. 7-221642, Japanese Unexamined Patent Publication No. 6-53799, or Japanese Unexamined Patent Publication No. 11-220393 discloses a circuit which enables an analog switch to operate at a low voltage by making signal potential at the gate electrode (boosting signal potential at the gate electrode to voltage) higher than power supply potential (in the case of an n-channel MOS field effect transistor) and by making voltage between the gate and source of the n-channel MOS field effect transistor (NMOS transistor) large.
With these circuits, the voltage of the gate of an NMOS transistor can be made higher than power supply voltage applied from the outside even if the power supply voltage is low. As a result, voltage between the gate and source of the NMOS transistor can be made large and the ON-state resistance of the NMOS transistor included in an analog switch can be reduced. Therefore, adding a comparatively simple circuit has enabled a circuit to operate at a high speed at a low voltage.
With the above conventional circuits, however, voltage between the gate and source of an NMOS transistor included in an analog switch may exceed the breakdown voltage, depending on circuit constants and operating conditions. That is to say, the improvement of the low-voltage characteristics of a circuit is restricted by the breakdown voltage of an NMOS transistor.
A circuit which Japanese Unexamined Patent Publication No. 6-140898 discloses is known as a device far reconciling the improvement of the low-voltage characteristics of an analog switch and restriction resulting from the breakdown voltage of an NMOS transistor.
FIG. 4 is a circuit diagram of a conventional analog switch circuit.
FIG. 4 is obtained by slightly simplifying the circuit Japanese Unexamined Patent Publication No. 6-140898 discloses.
In an analog switch circuit 2, an NMOS transistor NM1 and a PMOS transistor PM1 make up an analog switch section 100. Sources of the NMOS transistor NMI and the PMOS transistor PM1 are connected to a signal line 10 where an analog input signal (its potential is Vi) is input. Their drains are connected to an output signal line 20. A gate of the PMOS transistor PM1 is connected to a signal line 40 for inputting a gate signal. A gate of the NMOS transistor NM1 is connected to a capacitive element C1 and a drain of an NMOS transistor NM13. One side of the capacitive element C1 is connected to the output side of an inverter 600 via a signal line 71. The input side of the inverter 600 is connected to a delay circuit 610 via a signal line 72. The delay circuit 610 is connected to a delay circuit 611 via a signal line 73. A gate signal is input to the delay circuit 611. A source of an NMOS transistor NM14 is connected to the drain of the NMOS transistor NM13. A source of the NMOS transistor NM13 is connected to ground (GND). A gate of the NMOS transistor NM13 is connected to the signal line 40 where a gate signal is input. A drain of the NMOS transistor NM14 is connected to a source of an NMOS transistor NM15. The source of the NMOS transistor NM14 is connected to the drain of the NMOS transistor NM13 and the gate of the NMOS transistor NM1. A gate of the NMOS transistor NM14 is connected to the signal line 73. A drain of an NMOS transistor NM15 is connected to the signal line 10 where an analog input signal is input. The source of the NMOS transistor NM15 is connected to the drain of the NMOS transistor NM14. A gate of the NMOS transistor NM15 is connected to a signal line 74 which connects with the signal line 40, to which a gate signal is input, via an inverter 601.
Now, operation in the conventional analog switch circuit 2 will be described.
In the analog switch circuit 2, when the potential of the signal line 40 changes from the high level (H level) to the low level (L level) due to a gate signal input, the potential of the signal line 74 connected to the gate of the NMOS transistor NM15 changes from the L level to the H level and the NMOS transistor NM15 turns on. A change in the potential of the signal line 73 connected to the gate of the NMOS transistor NM14 will be delayed by the delay circuit 611. As a result, the signal line 73 keeps the H level at the time when the signal line 74 connected to the gate of the NMOS transistor NM15 changes to the H level. Therefore, the NMOS transistors NM14 and NM15 are in the ON state at the same time and the potential of a signal line 31 is charged to the input potential Vi of an analog input signal (at this time the potential of the signal line 40 is at the L level, so the NMOS transistor NM13 is in the OFF state).
After the potential of the signal line 31 is charged to the input potential Vi, the potential of the signal line 73 connected to the gate of the NMOS transistor NM14 changes to the L level. This change in the potential of the signal line 73 will be delayed by the delay circuit 611. The NMOS transistor NM14 turns off. Then the potential of the signal line 71 changes from the L level to the H level. This change will be delayed by the delay circuit 610 and inverter 600.
The amplitude of a signal on the signal line 71 equals power supply voltage VDD. When the potential of the signal line 71 changes from the L level to the H level, the NMOS transistor NM13 is in the OFF state. The potential of the signal line 31 therefore is boosted from Vi by VDD to (Vi+VDD).
As described above, the potential at the beginning of a voltage boost of the gate of the NMOS transistor NM1 included in the analog switch section 100 in the analog switch circuit 2 is set to Vi, being the potential of input to the analog switch. The potential of the gate of the analog switch is boosted by the capacitive element C1 to about (Vi+VDD). The potential of the source (or drain) of the NMOS transistor NM1 is input potential Vi, so voltage between the gate and source of the NMOS transistor NM1 included in the analog switch is about VDD. That is to say, voltage between the gate and source of the NMOS transistor NM1 will not exceed power supply voltage.
This prevents voltage between the gate and source of the NMOS transistor NM1 from exceeding the breakdown voltage. As a result, the improvement of low-voltage characteristics by a voltage boost and the observance of a restriction on breakdown voltage regardless of circuit constants or operating conditions have been reconciled.
With the conventional analog switch circuit 2, however, the PMOS transistor PM1 is put into the ON state by changing the potential of the gate of the PMOS transistor PM1 from the H level to the L level, the potential of the signal line 31 is charged to Vi, and then the potential of the signal line 31 is boosted to (Vi+VDD). As a result, the time when the NMOS transistor NM1 turns on will be delayed by time taken to charge the signal line 31 to Vi.
As described above, in the analog switch circuit 2, the potential of the signal line 31 rises from Vi by VDD to (Vi+VDD) when the potential of the signal line 71 changes from the L level to the H level. However, only if the capacitance of the capacitive element C1 is sufficiently greater than the parasitic capacitance of the signal line 31, the potential of the signal line 31 will rise by nearly VDD. It is assumed that the capacitance of the gate of the NMOS transistor NM1 is 0.2 pF, that the capacitance of the capacitive element C1 is 1.8 pF (nine times the capacitance of the gate of the NMOS transistor NM1), and that junction capacitance in the NMOS transistors NM13 and NM14 is negligible. If the amplitude of a signal on the signal line 71 is 3 V (VDD), then the potential of the signal line 31 will rise by 2.7 V ((9/10)×VDD). In the analog switch circuit 2, the capacitive element C1 the capacitance of which is sufficiently greater than that of the gate of the NMOS transistor NM1 must be charged to Vi by the NMOS transistors NM14 and NM15. Therefore, if the width (W) of the gates of the NMOS transistors NM14 and NM15 is small, it will take much time to charge the signal line 31 to Vi.
The second factor is the capacitance of a load on the signal line 20, being output from the analog switch section 100. If the capacitance of a load on output from the analog switch is great, usually the size of the NMOS transistor NM1 and PMOS transistor PM1 is designed to become large. It is assumed that the ratio of the capacitance of the gate of the NMOS transistor NM1 to the capacitance of a load on output from the analog switch is about one to ten. If the numeric value used in the above consideration is applied, the capacitance of a load on output from the analog switch is 2.0 pF (because the capacitance of the gate of the NMOS transistor NM1 is 0.2 pF). If the width of the gates of the NMOS transistors NM14 and NM15 in the analog switch circuit 2 is small, it will take much time to charge the signal line 31 to Vi. If the width of the gates of the NMOS transistors NM14 and NM15 is designed to become sufficiently large, input capacitance will be at least the sum of 2.0 pF, being the capacitance of a load on output from the analog switch, and 1.8 pF, being the capacitance of the capacitive element C1. That is to say, at a minimum, input capacitance will roughly double, resulting in longer delay time.
As described above, with the conventional analog switch circuit 2, the original purpose is to operate at a high speed at a low power supply voltage, but there are many factors in an increase in delay time.